Provide an understanding of digital sequential logic design practices and memory devices.Develop skill in the construction, test and debug of digital circuits.
Flip-Flop and Latch circuit elements:
D flip-Flops, synchronous behaviour. Latch element - transparent and latched behaviour. Preset and clear functions.
Applications:
Frequency division, Multi-bit registers, Shift registers,Serial/Parallel conversion, Ring counter, Johnson counter, Binary counters, MSIcounters. Basic FSM Techniques to design counters. External control ofcounters: Load, Clear, Up-Down and Enable signals. Cascaded counters.
Digital Logic IO characteristics:
IO Voltage levels. IO Currents and fanout. Different logic IO standards and their characteristics and uses. Totem pole, Open collector and tri-state outputs.
Interfacing to real world:
Debounce circuit. Schmitt trigger. Relay types and their uses. PWM techniques applied to LED brightness control. Shaft encoders and their use. Other interfaces of interest.
Static Timing Analysis:
Combinational and synchronous element timing characteristics. Analysing a multiple element circuit to determine critical timing path and maximum frequency of operation.
Memory Systems:
SRAM and DRAM structure, control lines, refreshing. Memorycells from latches, memory chips working together, general form of a memorysystem. Addressing memory using address decoders.
| Module Content & Assessment | |
|---|---|
| Assessment Breakdown | % |
| Other Assessment(s) | 40 |
| Formal Examination | 60 |