This module is a practical introduction to the Verilog hardware description language. Students will learn to write Verilog code, using FPGA Development tools, to model digital devices and systems. Problem solving will be explored while simulating digital designs and implementing them on a Field Programmable Gate Array (FPGA) prototyping board.
Introduction
Introduction to hardware description languages, Verilog, VHDL. The design flow. Structured design methodology, design partitioning and documentation.
FPGA
FPGA internal architecture. Prototyping board operation and resources. Technical and environmental advantages of using FPGAs.
Verilog
Verilog structure and syntax. Data types. Operators. Parameters. Logic values.Module, Always and Initial blocks. Arrays. if, case, switch, for, while statements.RTL, Structural. Delays.Concurrent and sequential operation. Blocking and non-blocking statements.Write verilog code the model digital designs such as Multiplexers, Decoders, Encoders, Adders, Counters, Latches, Flip Flops, Registers, Alu, Rom, Ram, Finite State Machines.
Implementation and verification
Functional simulation, timing simulation. Synthesis. Reading synthesis reports.Measuring delays. Writing test benches.
Scripts
Introduction to writing scripts to run simulation and implementation tools.
Project
Write reports according to specified guidelines. Document the design and verification process. Problem solving, communications, ethical considerations, team work.
| Module Content & Assessment | |
|---|---|
| Assessment Breakdown | % |
| Other Assessment(s) | 40 |
| Formal Examination | 60 |